PLL Webinar
A technical webinar focused on introducing students to Phase Locked Loops (PLL) and on-chip clock multipliers in modern electronics. The session combined theoretical concepts with practical design insights, enhancing understanding of ASIC design and CMOS fundamentals.
About This Event
Title of the event: PLL Webinar Objective: The objective of this event was to get the students acquainted with the On-Chip Clock Multiplier (PLL) on OSU180. BVP Optica organised an online workshop on Phased Locked Loop to get the students acquainted with the On-Chip Clock Multiplier (PLL) on OSU180. The workshop began with the introduction of ASIC design flow, PLLs and On-Chip Clock Multipliers. Theory and fundamental concepts like CMOS Implementation, Transistor Sizing, 2nd order control system, providing participants with both theoretical knowledge and practical insights.
Highlights
Understanding of On-Chip Clock Multipliers on OSU180.
Explanation of CMOS implementation and transistor sizing.
Online workshop format with detailed theoretical insights.
Enhanced understanding of VLSI and integrated circuit design.
Organized By
BVP Optica Team
Event Organizers
Event Details
Date & Time
2021-09-15 | 10:00 AM onwards
Location
Bharati Vidyapeeth's College of Engineering, New Delhi
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